The present invention relates generally to semiconductor devices, and more particularly to semiconductor memory devices.
In certain dynamic random access memories (DRAMs), it is necessary for the information stored in the memory cells to be periodically refreshed, since the memory cells can retain the information stored in them for only a limited time. The reason for this is that capacitors are used as memory cells for DRAMs. These capacitors discharge themselves after a specific time, as a result of unavoidable internal quiescent currents, so that the stored charges of the capacitors have to be regularly renewed. The period of time in which the memory cells hold their stored charge is known as its data retention time. The memory cells are, therefore, recharged at fixed predetermined time intervals, so-called refresh cycles. The pulse for recharging, the so-called refresh pulse, can be generated internally within the module, or else externally. In modern DRAMs, refresh cycles of at least 4096 refresh operations per 64 ms (refresh rate 6 k/64 ms) are customary.
The refresh cycle for the DRAM, e.g. the interval between the individual refresh pulses, must be chosen such that even the memory cell with the shortest retention time, which specifies how long the memory content can be retained in the associated cell, is refreshed again in due time. The conventional refresh method in the case of DRAMs, therefore, has the consequence that even memory cells with longer retention times are refreshed again prematurely. This leads to an unnecessarily high current consumption in the DRAM, and shortens, in particular, the operating duration of accumulator- or battery-operated computers having such DRAMs. Since the normal writing and reading operations of the DRAM are interrupted during the refresh operation, e.g., by the presence of a so-called wait command, at the processor, which controls the DRAM, the availability of the DRAM is also reduced by the short refresh cycles required for the memory cells.
Desirable in the art of semiconductor memory design are improved memory refresh methods and circuits with which better control of the power consumption may be achieved.